多晶硅薄膜晶体管RPI模型的直流参数提取

多晶硅薄膜晶体管(TFT)在有源液晶显示器中的应用充分显示了它的性能优点。对多晶硅TFT进行模型分析和参数提取是理解多晶硅TFT工作原理和指导制备的有效途径。归纳并讨论了多晶硅薄膜晶体管RPI模型直流参数的提取策略。此参数提取步骤简单,并能准确地提取所有工作区的基本直流参数,如阈值电压、漏源区串联寄生电阻、有效沟道长度、迁移率等。参数提取的方法将为RPI模型的电路仿真提供有益的参考。最后,提出了改进RPI模型参数提取策略的方向,包括提高泄漏电流参数、迁移率参数的准确度等。     

Stackable nonvolatile memory with ultra thin polysilicon film and low-leakage (Ti, Dy)xOy for low processing temperature and low operating voltages

We report the fabrication process as well as material and electrical characterization of ultra thin body (UTB) thin film transistors (TFTs) for stackable nonvolatile memories by using in situ phosphorous doped low-temperature polysilicon followed by the chemical mechanical polishing (CMP) process. The resulting polysilicon film is about 13 nm thick with approximately 10¹⁹ cm⁻³ doping. Root mean square surface roughness below 1 nm is achieved. Metal nanocrystals and high-k dielectric are selected for storage nodes and tunneling barriers to achieve low operating voltages. The number density and average diameter of nanocrystals embedded in the gate stack are 7.5 × 10¹¹ cm⁻² and 5.8 nm, respectively. Furthermore, scanning transmission electron microscopy (STEM), convergent beam electron diffraction (CBED) and electron energy loss spectroscopy (EELS) are performed for material characterization. The dielectric constant of the (Ti, Dy)_xO_y film is 35, and the off-state leakage current at −1 V bias and 2.8 nm equivalent oxide thickness is 5 × 10⁻⁷ A/cm². We obtain a memory window of about 0.95 V with ±6 V program/erase voltages. Our results show that UTB TFT is a promising candidate for the three-dimensional integration in high-density nonvolatile memory applications.     

TFT-LCD工厂能源消费结构及用能特点分析

TFT-LCD工厂具有投资高、建筑体量大、能源消耗量大的特点。为了在工厂设计、建设、运营阶段有的放矢地做好节能降耗工作,针对重点耗能工序、耗能设备以及影响能耗的关键因素,采取科学、合理、可行的节能措施和节能工程,从而达到更好的节能效果。本文对TFT-LCD工厂能源消耗种类、能源消费结构及能源分布特点、主要能源加工转换过程中的能量平衡、能效指标等进行了研究分析。总结我院多年来完成的同类项目经验数据,通过层次分析法、能量平衡分析方法、标准对照方法等对主要用能体系及用能特点进行深入剖析。分析结果表明,电力是TFT-LCD项目消耗量最大的能源,约占全厂综合能耗的75%以上,其中工艺生产设备电力消耗约占全厂用电的45%~50%,阵列为最主要的工艺耗能工序,厂务系统中冷水机组等动力设备是主要耗能设备;氮气是消耗量最大的耗能工质,约占全厂综合能耗的20%。能源消费结构及用能特点基本符合此类工厂实际运行特点,对TFT-LCD面板项目节能具有较高的指导价值。     

电极在TFT玻璃生产中的应用

该文阐述了TFT玻璃窑炉使用电极的原因与要求。通过介绍熔制玻璃用的几种电极和TFT玻璃窑炉中电极的安装、分布方式,对TFT玻璃生产中电极的选择进行了分析,并提出了使用电极的注意事项。     

Characterization of crystallographic properties of SMC poly Si using electron backscattered diffraction

Crystallographic properties of silicide mediated crystallization (SMC) polycrystalline silicon (poly Si) and excimer laser annealing (ELA) poly Si were studied by electron backscattered diffraction. Large‐grain sized poly Si with a large fraction of low‐angle grain boundaries was acquired by SMC, and small‐grain sized poly Si with high‐angle grain boundaries especially around 60° was acquired by ELA. The thin film transistor (TFT) device characteristics were investigated in view of short‐range crystallinity (pattern quality) and long‐range crystallinity (misorientation distribution) of the specimens. Short‐range crystallinity did not significantly affect the TFT device characteristics, and long‐range crystallinity considering the low energy level of special boundaries could be better related to the TFT device characteristics of poly Si.     

A dry-patterned Cu(Mg) alloy film as a gate electrode in a thin-film transistor liquid crystal display

The annealing of a Cu(4.5at.%Mg)/SiO₂/Si structure in ambient O₂ at 10 mtorr and 300–500°C allows for the out-diffusion of the Mg to the Cu surface, forming a thin MgO (15 nm) layer on the surface. The surface MgO layer was patterned and successfully served as a hard mask for the subsequent dry etching of the underlying Mg-depleted Cu films using an O₂ plasma and hexafluoroacetylacetone (H(hfac)) chemistry. The resultant MgO/Cu structure, with a taper slope of about 30°, shows the feasibility of dry etching of Cu(Mg) alloy films using a surface MgO mask scheme. A dry-etched Cu(4.5at.%Mg) gate a-Si:H thin-film transistor (TFT) has a field-effect mobility of 0.86 cm²/Vs, a subthreshold swing of 1.08 V/dec, and a threshold voltage of 5.7 V. A novel process for the dry etching of Cu(Mg) alloy films that eliminates the use of a hard mask, such as Ti, and results in a reduction in the process steps is reported for the first time in this work.     

溅射SiGe薄膜及其等时等温退火效应

分别在n-Si(100)和SiO2衬底上用离子束溅射法淀积SiGe薄膜.用俄歇电子谱测定薄膜Ge含量为15%～16%.对样品进行常规炉退火以考察退火温度和时间对薄膜结晶度的影响.采用X射线衍射确定薄膜物相.发现在同样退火条件下,SiGe在n-Si衬底上比SiO2上有更高的结晶度.通过曲线拟合,得到平均晶粒尺寸与退火温度和时间的依赖关系分别是自然指数和近线性的抛物线函数.推断出溅射SiGe薄膜的热退火结晶可能是晶粒生长控制过程.     

a-Si:H TFT亚阈值区SPICE模型的研究

研究了将非晶硅薄膜晶体管（a-Si：H TFT）在电路模拟程序（SPICE）中使用的亚阈值区模型,将亚阈值区分为亚阈值前区和亚阈值后区并建立了模型,对比了不同模型下的模拟结果,发现亚阈值区的TFT特性依赖于材料性质,而且亚阈值前区和亚阈值后区的特性受栅源电压Vcs和漏源电压V DS的影响,呈指数变化。提出的新模型考虑了前界面态、后界面态、局域态、材料及制作工艺等因素,体现了该区域电流对漏源电压Vvs强烈的依赖关系。使用新模型对实验数据的拟合结果优于以往的模型,能够比较精确地模拟亚阈值区的特性,可用来预测a-Si：H TFT的性能．对TFT阵列的模拟设计具有重要价值。     

Effects of oxygen on crystallization of amorphous silicon films and polysilicon TFT characteristics

Oxygen ions were implanted into the amorphous silicon film deposited at 540°C in order to study the effects of oxygen on the solid phase crystallization of silicon films. The resulting films were investigated using transmission electron microscopy, x-ray diffraction (XRD), and also by measuring the electrical characteristics of polycrystalline silicon thin film transistors (TFTs) fabricated in the crystallized films. The development of {111} texture as a function of annealing time is similar to films implanted with Si, with higher oxygen samples showing more texture. Transmission electron microscopy shows that the grain size of completely crystallized films varies little with oxygen concentration. The electrical performances of TFTs are found to degrade with increasing oxygen dose. The trap state density increases from 5.6 × 10¹²/cm² to 9.5 × 10¹²/cm² with increasing oxygen dose. It is concluded that for a high performance TFT, oxygen incorporation in the Si film should be kept to 10¹⁹/cm³ or less.     

The Bipolar Field-Effect Transistor: ⅩⅢ. Physical Realizations of the Transistor and Circuits (One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its one-transistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These ex-amples include the one-MOS-gate on semi-infinite thick impure base transistor (the bulk transistor) and the impure-thin-base Silicon-on-Insulator (SOI) transistor and the two-MOS-gates on thin base transistors (the FinFET and the Thin Film Transistor TFT). Figures are given with the cross-section views containing the electron and hole concen-tration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.